Computer graphics display systems, e.g., CAD/CAM graphics workstations, are widely used to generate and display two-dimensional images of three-dimensional objects for scientific, engineering, manufacturing and other applications. In such graphics systems, digital representations of computer generated images conventionally reside in an array of video random access memory (VRAM), which collectively embody the system frame buffer. The rate at which the frame buffer can be updated is a critical parameter in the performance of the entire graphics system. In addition, with the ever increasing use of graphics workstations there is a need to perform ever more varied color renderings, which conventionally negatively impact system performance.
Dynamic random access memories (DRAMs) are the memory of choice for many computer memory systems. In most DRAMs, single-bit storage elements or cells are arranged in an array fashion. The array is composed of words and columns, where rows are referred to as "word lines" and columns are referred to as "bit lines". Data lines transfer data to and from the storage arrays. In conventional read and write operations, one memory cell in each column is connected to its corresponding bit line. A sense amplifier attached to each bit line amplifies and restores the signals placed on the bit line during a read operation. In a DRAM chip, read and write operations each require two steps. The first step is to select the row, which is done by asserting a row address strobe (RAS) while the desired row address is on the address inputs. An on-chip row decoder then produces a vector whose bits are zero everywhere except for a one at a selected row. This bit vector determines which row of storage cells is connected to the bit lines and their associated sense amplifiers.
The second step is to select the column, which is done by asserting a column address strobe (CAS) and a read-write signal while the desired column address is on the address inputs. The column address selects a bit from the active row of memory in each array. The selected bits are either buffered for output (during read operations) or assigned values received from the data inputs (during write operations).
A VRAM is a particular type of DRAM designed specifically to allow video scanout to be independent of other frame-buffer operations in a video display system. A VRAM chip is similar to a conventional DRAM chip but contains a parallel-in/serial-out data register connected to a second data port. The serial register can be as wide as the memory array and can be parallel loaded by asserting the transfer signal while a row of memory is being read. The serial register has its own data clock, enabling it to transfer data out of the chip at high speeds. The serial register and port effectively provide a second serial port to the memory array. If this port is used for video scanout, scanout can occur asynchronously to normal reads from the writes to the chip, virtually eliminating any video scanout problem.
One approach to enhancing performance of a DRAM or VRAM is to incorporate a block write feature (and/or a flash write feature) into the memory circuit. A block write allows data to be simultaneously written to a set of bit lines along an accessed word line. In the existing art, a block write function is accomplished by accessing the word lines for a normal read, writing the data to selected bit lines by overpowering the associated sense amplifiers, and then carrying out the normal restore cycle. One preferred approach to block overwriting is described in a co-pending application entitled "Semiconductor Memory Circuit With Block Overwrite", Ser. No. 08/165,778, assigned to the same assignee as the present invention.
Traditionally, VRAM chips incorporate a single color register which serves to temporarily hold color data to be written during a block write or flash write operation. Unfortunately, with a single color register, only one color may be written at RAS cycle time into the memory array. Thus, writing of multiple colors is inconvenient and time consuming because each color must be separately loaded into the color register between write operations.
The invention described herein presents a technique for significantly enhancing performance of a video RAM when multiple color renderings are desired of the graphics system.